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ICs for Communications
Memory Time Switch Extended Large MTSXL PEB 2447 Version 1.2
Data Sheet 03.97
T2447-XV12-D2-7600
PEB 2447 Revision History: Previous Version: Page Page (in previous (in current Version) Version) 32
Current Version: 03.97 (Editorial Update) 01.95 Subjects (major changes since last revision)
Register Address Arrangement (new)
Edition 03.97 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
PEB 2447
Table of Contents 1 1.1 1.2 1.3 1.4 1.5 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.3 2.3.1 2.3.2 2.3.3 2.3.4 3 3.1 3.2 3.3 3.4 3.5 3.6 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 5 6
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 General Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Control Memory Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Evaluate Frame Measurement Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 MTSXL Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Boundary Scan and TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Use of Built in Selftest via the Boundary Scan Interface . . . . . . . . . . . . . . . .19 IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Indirect Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Frame Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Input Offset and Output Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Frame Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Register Address Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Mode Register (MODR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Command Register (CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Status Register (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Interrupt Status Register (ISTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Memory Access Address/Code Register High (MACH) . . . . . . . . . . . . . . . . .37 Memory Access Address Register Low (MAAL) . . . . . . . . . . . . . . . . . . . . . .38 Memory Read Data Register Low (MRDL) . . . . . . . . . . . . . . . . . . . . . . . . . .39 Memory Read Data Register High (MRDH) . . . . . . . . . . . . . . . . . . . . . . . . . .39 Memory Write Data Register Low (MWDL) . . . . . . . . . . . . . . . . . . . . . . . . . .39 Memory Write Data Register High (MWDH) . . . . . . . . . . . . . . . . . . . . . . . . .40 Input Clock Shift Register Bank ICSR (15:0) . . . . . . . . . . . . . . . . . . . . . . . . .41 Output Clock Shift Register (OSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Test Register (TSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Frame Evaluation Register Low (FERL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Frame Evaluation Register High (FERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
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Memory Time Switch Extended Large MTSXL
PEB 2447
Version 1.2 1 1.1 Overview Features
CMOS IC
* Non blocking time/space switch for 4.096- or 8.192-Mbit/s PCM systems * Device clock 16.384 MHz * Switching of up to 2048 incoming PCM channels to up to 2048 outgoing PCM channels P-MQFP-100-2 * 32 input and 32 output PCM lines * Tristate function for further expansion and tandem operation * P read access to PCM data * Programmable clock shift with half clock step resolution for input and output * Individual line delay measurement for 6 additional inputs * Individual input offset programmable for 16 PCM inputs * Boundary scan (fully IEEE1149.1 compatible) * Built-in selftest (also usable via boundary scan interface) * 8-bit Intel type demultiplexed P interface * All registers accessible by direct addressing * In-operation adjustment of bit sampling without bit errors * Low power consumption * Single 5 V power supply
Type PEB 2447 H
Ordering Code Q67103-H6594
Package P-MQFP-100-2
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Overview 1.2 Logic Symbol
Figure 1 Functional Symbol 1.3 General Device Overview
The Siemens Memory Time Switch Extended Large MTSXL (PEB 2447) is a capacity expansion of the MTSL (PEB 2047). It is a monolithic CMOS switching device capable of connecting maximally 2048 PCM input time slots to 2048 output time slots. In order to manage the problem of different line delays, six additional FS inputs can be used as frame measurement inputs and 16 different input offsets of PCM frames are allowed. Thus a frame wander can be compensated by adjusting the input offset during operation. A special circuitry guarantees that no bit error will occur, when reprogramming the input offsets. The MTSXL on chip connection memory and data memory are accessed via the 8-bit standard P interface (Intel demultiplexed type). A built-in selftest mechanism - also activated by the P - ensures proper device operation in the system. The PEB 2447 is fabricated using the advanced CMOS technology from Siemens and is mounted in a P-MQFP-100-2 package. Inputs and outputs are TTL compatible.
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Overview 1.4 Pin Configuration (top view)
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 IN17 IN18 IN19 Index Marking
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 90 41 PEB 2447 91 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TCK TDI TMS TDO INT OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 VSS VDD OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22
OUT23 OUT24 OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 OUT31 VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 SP
IN20 IN21 IN22 IN23 IN24 IN25 IN26 IN27 IN28 IN29 IN30 IN31 VDD VSS CLK FS0 FS1 FS2 FS3 FS4 FS5 A4 A3 A2 A1 A0 CS RES WR RD
ITP09593
Figure 2
1.5
Pin Definitions and Functions Input (I) Output (O) Tristate (T) I Function
Pin No. Symbol
14 41 67 13 40 66
VSS
Ground (0 V)
VDD
I
Supply Voltage: 5 V + 5 %.
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Overview 1.5 Pin Definitions and Functions (cont'd) Input (I) Output (O) Tristate (T) I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Function
Pin No. Symbol
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 15
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 IN17 IN18 IN19 IN20 IN21 IN22 IN23 IN24 IN25 IN26 IN27 IN28 IN29 IN30 IN31 CLK
PCM Input Ports: Serial data is received at standard TTL levels.
Clock: 16.384 MHz device clock.
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Overview 1.5 Pin Definitions and Functions (cont'd) Input (I) Output (O) Tristate (T) I I I I I I I I I I I I I I I I I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T Function
Pin No. Symbol
16 17 18 19 20 21 26 25 24 23 22 27 28 29 30 31 39 38 37 36 35 34 33 32
FS0 FS1 FS2 FS3 FS4 FS5 A0 A1 A2 A3 A4 CS RES WR RD SP D0 D1 D2 D3 D4 D5 D6 D7
Frame Measuring Inputs: These inputs are used as frame evaluation inputs.
Address Bus Bit 0 to 4: These inputs interface to the systems address bus to select an internal register for a read or write access.
Chip Select: (low active) A low level selects the MTSXL for a register access operation. Reset: A high signal on this Input forces the MTSXL into reset state. Write: (low active) This signal indicates a write operation. Read: (low active) This signal indicates a read operation. Synchronization Pulse: The MTSXL is synchronized to the PCM system via this line. Data Bus: These pins transfer data between the P and the MTSXL.
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Overview 1.5 Pin Definitions and Functions (cont'd) Input (I) Output (O) Tristate (T) O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O/T O Interrupt Line: Active low. (Open Drain) Reset when reading ISTA O/T Test Data Output: In the appropriate TAP controller state test data, an instruction or the selftest result is shifted out via this line.
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Pin No. Symbol
Function
75 74 73 72 71 70 69 68 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 76 77
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 OUT31 INT TDO
PCM Output Port: Serial data is sent by these lines. These pins can be tristated.
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PEB 2447
Overview 1.5 Pin Definitions and Functions (cont'd) Input (I) Output (O) Tristate (T) I (internal pull-up) I (internal pull-up) I Function
Pin No. Symbol
78
TMS
Test Mode Select: 0 -> 1 transitions on this pin are required to step through the TAP controller state machine. Test Data Input: In the appropriate TAP controller state test data or an instruction is shifted in via this line. Test Clock: Single rate test data clock (6.25 MHz)
79
TDI
80
TCK
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Functional Description 2 Functional Description
The MTSXL is a memory time switch device. Operating with a device clock of 16.384 MHz it can connect any of 2048 PCM input channels to any of 2048 output channels. A general block diagram of the MTSXL is shown in figure 3. 2.1 General Operation
The input information of a complete frame is stored twice in the two on-chip 16-kbit data memories DM 0 and DM 1 (Data Memory 0 and Data Memory 1). The incoming 2048 channels of 8 bits each are written in sequence into fixed positions of DM 0 and DM 1. This is controlled by the input counter in the timing control block with a 8 kHz repetition rate. For outputting, two connection memories (CM 0 and CM 1) are read in sequence synchronously. Each entry in the connection memory CM 0 / CM 1 points to a location in data memory DM 0 / DM 1. The byte in this data memory location is transferred into the current output time slot. The read access to the CM's is controlled by an output counter. CM 0 supplies the PCM data for outputs OUT0 to OUT15, CM 1 supplies the PCM data for outputs OUT16 to OUT31.
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Functional Description
Figure 3 Block Diagram of MTSXL The synchronization of the input and output counters is achieved by a rising edge of the sync pulse SP, which is always sampled with the falling edge of the device clock. Different modes of operation are configurable at the PCM interfaces (see table 9). Furthermore, 16 PCM input lines can be aligned with individual clock shift values to compensate different line delays. If 32 inputs are used, one clock shift value controls two ports at the same time. Shifting of the output frame is also possible, but all output lines are affected the same way. The input lines FS0 to FS5 are used as frame measurement inputs. After synchronizing the device by the SP pulse the FS inputs can be evaluated on a per port basis. This evaluation procedure is started by a microprocessor command. As a result the input counter value on the rising edge of the FS signal can be read from an internal register. Thus delay compensation is easily managed by programming appropriate clock shift values and/or a possible software offset.
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Functional Description During operation of the chip a frame length check is also supplied, which controls correct synchronization by the SP pulse and generates an interrupt in case of lost or achieved synchronization. The unused output ports are tristated by mode selection, whereas unused time slots are tristated by an additional bit in the control memory. By using this tristate capability the MTSXL can be easily expanded to a time switch of any size. The standard 8-bit P interface can communicate with Intel demultiplexed microprocessors. It gives access to the internal registers and to the control and data memory. All registers are directly addressable. The memories are accessed by a simple four byte indirect access method. 2.2 Special Functions
The activity of all special functions can be read in the status register. Completion of these functions is indicated by interrupts. 2.2.1 Control Memory Reset
Initialization of the device after a hardware reset (RES) is easily done with a P command "control memory reset". After finishing this procedure all control memory channels contain the information "tristated". Apart from this tristate information the contents of the C Memory is undefined. 2.2.2 Evaluate Frame Measurement Signal
A command including the address (0 ... 5) will be given by the P. The rising edge of the corresponding frame measurement signal (FS0 ... FS5) will be evaluated. The exact timing of the FS edge can then be read from an internal 12-bit register (resolution of a complete 8 kHz frame in half 16 MHz clock periods). 2.2.3 MTSXL Selftest
The switching path of the MTSXL including input buffer, data memory, control memory, output buffer and timing control can be tested in the system by a 2-step built-in selftest. Activating this mechanism takes 2 x 0.625 ms (16.384 MHz). Finally the result "selftest ok/selftest not ok" can be read from the internal status register. After test completion the control memory has also been reset (contains the information tristated). The selftest can also be started and checked via the boundary scan interface.
Note: For correct execution of the built-in selftest the MTSXL needs a value of ICSR = 00. If MODR:PSB = 0 (e.g. after hardware reset) this value is programmed automatically after start of the selftest procedure. If ICSR does not contain "00" with MODR:PSB = 1 the selftest will fail.
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Functional Description 2.3 2.3.1 Boundary Scan and TAP Controller Boundary Scan
The MTSXL provides fully IEEE Std. 1149.1 compatible boundary scan support consisting of - - - - a complete boundary scan a test access port controller (TAP controller) four dedicated pins (TCK, TMS, TDI, TDO) a 32 bit IDCODE register
All pins except power supply and ground are included in the boundary scan. Depending on the pin functionality one, two or three boundary scan cells are provided: Table 1 Boundary Scan Cell Type Pin Type Input Output I/O Number of Boundary Scan Cells 1 2 3 Usage Input Output, enable Input, output, enable
When the TAP controller is in the appropriate mode data is shifted into / out of the boundary scan via the pins TDI / TDO using the 6.25 MHz clock on pin TCK. The MTSXL pins are included in the boundary scan in the following sequence: Table 2 Boundary Scan Sequence Boundary Scan Number TDI -> 1 2 3 4 5 6 7 8 9 10 11 Pin Number 81 82 83 84 85 86 87 88 89 90 91 Pin Name IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 Type Number of Scan Cells I 1 I I I I I I I I I I 1 1 1 1 1 1 1 1 1 1 Default Value 0 0 1 0 0 0 0 0 0 0 0
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Functional Description Table 2 Boundary Scan Sequence (cont'd) Boundary Scan Number TDI -> 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Number 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 Pin Name IN11 IN12 IN13 IN14 IN15 IN16 IN17 IN18 IN19 IN20 IN21 IN22 IN23 IN24 IN25 IN26 IN27 IN28 IN29 IN30 IN31 CLK FS0 FS1 FS2 FS3 FS4 FS5 A4 A3 A2 Type Number of Scan Cells I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Default Value 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
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Functional Description Table 2 Boundary Scan Sequence (cont'd) Boundary Scan Number TDI -> 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Pin Number 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Pin Name A1 A0 CS RES WR RD SP AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 Type Number of Scan Cells I I I I I I I IO IO IO IO IO IO IO IO O O O O O O O O O O O O O O O O 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Default Value 0 0 0 0 0 0 0 000 000 000 000 000 000 000 000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Functional Description Table 2 Boundary Scan Sequence (cont'd) Boundary Scan Number TDI -> 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Pin Number 58 59 60 61 62 63 64 65 68 69 70 71 72 73 74 75 76 Pin Name OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 INT Type Number of Scan Cells O O O O O O O O O O O O O O O O O 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Default Value 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Functional Description 2.3.2 TAP Controller
The TAP controller implements a state machine defined in the JTAG standard IEEE1149.1. The instruction register of the controller is extended to 4 bits in order to increase the number of instructions. This is necessary for the use of the build in selftest procedure via the boundary scan interface: Table 3 Instruction Code of 4 Bit TAP Controller Instruction EXTEST INTEST SAMPLE / PRELOAD IDCODE BYPASS TAP_TEST1: Start built in self test TAP_TEST2: Write selftest control register TAP_TEST3 TAP_TEST4 TAP_TEST5 TAP_TEST6 TAP_TEST7 TAP_TEST8 Code 0000 0001 0010 0011 11xx 0100 0101 0110 0111 1000 1001 1010 1011
The standard instructions are implemented according to the JTAG standard, just the instruction register is extended to 4 bits. At the new instructions TAP_TEST1.. 8 special internal test signals are activated during the state "RUN TEST / IDLE". The MTSXL only uses TAP_TEST1 and TAP_TEST2 according to table 3.
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Functional Description The extended TAP controller uses a modified data path: Table 4 Data Path of 4 Bit TAP Controller Instruction Code 11xx 00xx 0011 01xx 10xx Input TDI BSOUT BSOUT_ID TDI2: STAR:STOK (internal) TDI3: VSS (not used, internal) Data Path Output TDO TDO TDO TDO TDO
When TAP_TEST1 / 2 is activated the data path is set to shift the result of the selftest procedure (bit STAR:STOK) out through the TDO pin. 2.3.3 Use of Built in Selftest via the Boundary Scan Interface
The built in self test is used by the following steps: - The instruction TAP_TEST2 is shifted into the TAP controller (see figure 4) - STP command is shifted into the selftest control register (see table 5 and figure 5) - The instruction TAP_TEST1 is shifted into the TAP controller to start the selftest (see figure 6) after 10240 TCK periods: - Bit STAR:STOK can be shifted out (see figure 7). Table 5 4 Bit Selftest Control Register Bit ST [0] ST [1] ST [2] ST [3] Function CMDR:STP0 CMDR:STP1 CMDR:STP2 "1" built in selftest "0" no built in selftest
Note: ST [2:0] represent the bits CMDR:STP2..0 but do not overwrite them.
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Functional Description The TAP controller state machine passes through the different states according to figures 4 to 7. Table 6 States of TAP Controller (explanation for figures 4 to 7) Controller State Exit2-DR Exit1-DR Shift-DR Pause-DR Select-IR-Scan Update-DR Capture-DR Select-DR-Scan Exit2-IR Exit1-IR Shift-IR Pause-IR Run-Test / Idle Update-IR Capture-IR Test-Logic-Reset State Code 0 1 2 3 4 5 6 7 8 9 A B C D E F
Note: The state coding is only described for explanation purposes, it is externally not visible.
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Functional Description
Figure 4 Starting Instruction "TAP_TEST2" (code 0101)
Figure 5 Writing Selftest Control Register
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Functional Description
Figure 6 Start of Built in Selftest (instruction TAP_TEST1, code 0100)
Figure 7 Readout of Selftest Result (after 10240 TCK periods)
Note: After the use of the selftest procedure over the P Interface or the boundary scan interface a hardware reset is necessary before the selftest procedure can be started again over the other interface.
2.3.4 IDCODE
The manufacturer code for MTSXL is according to table 2: V1.2: 0010 0000 0000 0010 0101 0000 1000 001 1
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Operational Description 3 3.1 Operational Description Initialization Procedure
For a proper initialization of the MTSXL the following procedure is recommended: First a reset pulse (RES) of at least two CLK clock periods has to be applied. All registers contain now their reset values. In the next step the connection memories CM0/1 are initialized by the commands CMDR:STP (1:0) = 01 (CM reset) or CMDR:STP (2:0) = 011 / 111 (MTSXL selftest). After having programmed a CM reset command, it takes 4096 clock periods until all tristate control entries in the CM contain the value "1" (tristated). If a selftest command was given, it takes 10 240 clock periods to achieve the same effect. Furthermore the register bit STAR:STOK (selftest o.k.) should read "1" in this case, in order to prove that there is no fault on the chip. The selftest command must be given twice: the upper half of data memory (DM0, DM1) is tested when setting CMDR:STP (2:1) = 01, the lower half of DM0, DM1 is tested by setting CMDR:STP (2:1) = 11 (see table 10). The activity of the procedures can be monitored in STAR:PACT and an interrupt will indicate their completion. In all cases it is important, that the outputs are tristated by MODR:PSB = 0. 3.2 Operation Mode
The operation mode of the device is fixed by programming MODR:MD (1:0) (see table 9). 3.3 Indirect Access Registers
The connection memories and data memories are accessible through the indirect access registers MACH, MAAL, MRDH, MRDL, MWDH and MWDL. An indirect access is actually started by writing register MACH (Memory Access Address/Code Register High). The code value inherent in this register defines, what action has to be performed. The low byte of the complete access address must be programmed to MAAL (Memory Access Address Register Low) before writing to MACH. If data are necessary to perform the access (e.g. in write operations), they have to be entered into MWDH (Memory Write Data Register High) and MWDL (Memory Write Data Register Low) before. In read accesses the corresponding registers MRDH (Memory Read Data Register High) and MRDL (Memory Read Data Register Low) contain the required information after the internal read process is completed.
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Operational Description Typical Write Operation: WR MWDL WR MWDH WR MAAL WR MACH RD STAR; STAR:MAC = 0 RD MRDL RD MRDH Typical Read Operation: WR MAAL WR MACH RD STAR; STAR:MAC = 0
3.4
Frame Evaluation
If the device is in synchronized state (STAR:PSS = 1) and for example the command "frame evaluation at FS5" (CMDR = 58H) is programmed, the second following rising edge of FS5 is evaluated and creates the following result in register FERH:FERL (see also table 15):
Figure 8 Frame Evaluation
Note: The frame evaluation procedure gives (roughly) the number to be programmed in ICSR (after inversion of FER0): FEV 11..1 give the number of complete CLK periods; FEV 0 gives the sampling edge (falling / rising). Due to the internal delay in the MTSXL the sampling region and therefor the result in FEV 11..1 is shifted against CLK for a time "X" which is uncertain between 0 < X < 13 ns. If the rising edge of FS occurs in that uncertain region the value of FER 11..1 might vary + 1 (FER 0 inverted before!).
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Operational Description 3.5 Input Offset and Output Offset
Based on the results of the frame evaluation procedures the input offsets can be adjusted by programming ICSR 7..0 corresponding to inputs IN 7..0. If data oversampling is used, the values of ICSR 7..0 can be adjusted within some limits during operation without producing bit errors: - clockrate = 2 x datarate possible adjustment is one half clock period forward or backward. - clockrate = 4 x datarate possible adjustment is one clock period backward or two clock periods forward.
Figure 9 Input Timing
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Operational Description
Figure 10 Output Timing The output offset is the same for all output lines and is fixed in register OCSR.
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Operational Description 3.6 Frame Delay
Figure 11 shows a functional description of the Serial Input, Data Memory and Serial Output.
Figure 11 Internal Processing of Serial Data In mode 0 for example inputs 0 and 8 are both connected to the input shift register. In mode 1 and 3 only input 0 is used and two time slots are always processed together.
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Operational Description
Figure 12 Internal Control Signals Mode 0 (OCSR = 0)
Note: O_SYN is a control signal for the synchronization of RD and WR access to the data memory and not important for the external functionality. O_SYN frequency is fCLK / 2.
This figure shows that the inputs IN0 .. IN15 are written into the data memory at the same time whereas IN16 .. IN31 are written one O_SYN period (= 2 CLK periods) later. The value of ICSR 0..15 shifts the sampling points and the signal "Ld Inp Buffer 1" later in time (rightwards), the signals "Ld Inp Buffer 2" and "Wr S Memory" remain constant. In this example with OCSR = 0 the lower Inputs IN0 .. IN15 are written into data memory before Out15 (and Out31) is read. With OCSR > 0 all Output Signals (Ld Outp Buffer and following) including the data (OUT0..15) on the internal data transfer bus is shifted earlier in time (leftwards). Therefor the data is read out of the data memory earlier. Due to the internal timing the frame delay is depending on the programmed input / output time slots and OCSR. The internal delay (number of time slots) can be deduced from figure 12 and is shown in table 7.
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Operational Description If the offset of output time slot to input time slot is greater or equal to the internal delay due to table 7 the transmission of data is within the same frame (frame delay 0). If the offset is smaller or even negative the transmission is in the next frame (frame delay 1). Frame delay 1 also occurs when the programmed connection overrides the frame end (TS63 in Mode 0). If the offset is smaller and overrides the frame end at the same time the frame delay is 2. Table 7 Time Slots Delay Mode 0 OCS(4:0) IN Outputs 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 . . 0 - 15 0 - 15 0 - 15 0 - 15 3 3 4 4 3 3 3 3 3 4 4 4 3 3 3 3 3 3 3 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 3 3 3 3 3 3 3 16 - 31 3 16 - 31 4 16 - 31 4 16 - 31 4
Maximum delay 4 time slots IN1 ts1 IN1 ts1 -> OUT1 ts 5 -> OUT1 ts 3 (Offset 4ts) : (Offset 2ts) : (Offset 2ts) : (Offset 3ts) : frame delay 0 frame delay 1 frame delay 1 frame delay 2
Examples: Connection (OCSR=0)
IN1 ts62 -> OUT31 ts 0 IN1 ts62 -> OUT1 ts 1
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Operational Description
Figure 13 Internal Control Signals Mode 1/3 (OCSR = 0)
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Operational Description Table 8 Time Slot Delay Mode 1 / 3 (deduced from figure 13, only Input time slots 0, 2, 4,..) OCS(4:0) IN 0 16 0 1 2 3 . . 0-7 16 - 23 0-7 16 - 23 0-7 16 - 23 0-7 16 - 23 5 5 5 6 6 6 6 6 1 17 5 5 5 5 5 6 6 6 2 18 5 5 5 5 5 5 5 6 3 19 5 5 5 5 5 5 5 5 Outputs 4 20 5 5 5 5 5 5 5 5 5 21 5 5 5 5 5 5 5 5 6 22 5 5 5 5 5 5 5 5 7 23 4 5 5 5 5 5 5 5
Maximum delay 6 time slots
Note: The time slot delays given in table 8 are valid only for even input time slots; for odd input time slots all delays have to be reduced by 1 time slots.
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Detailed Register Description 4 4.1 Reg. Name MODR CMDR STAR ISTA MASK MACH MAAL MRDL MRDH MWDL MWDH ICSR (15:0) OSCR TSTR FERL FERH Detailed Register Description Register Address Arrangement Access RD/WR WR RD RD WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD RD Address A4..0 00H 01H 01H 02H 02H 04H 03H 05H 06H 07H 08H Reset Value 00H 00H 01H 00H 0FH 0XH XXH XXH 0XH XXH XXH Comment Mode register Command register Status register Interrupt status register Mask register Memory access address/code register high Memory access address register low Memory read data register low Memory read data register high Memory write data register low Memory write data register high Input clock shift register bank Output clock shift register Test register Frame evaluation register low Frame evaluation register high Refer to page 33 34 35 36 37 37 38 39 39 39 40 41 42 42 43 43
10H .. 1FH 00H 0BH 0CH 0EH 0FH 00H C0H XXH XXH
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Detailed Register Description 4.2 Mode Register (MODR) 00H 00H Bit 0 0 0 0 0 0 MD1 MD0
Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 PSB PSB MD1 ... MD0 Table 9 Operation Modes Operation Mode Mode 0 Mode 1 Mode 3 Mode Bits MD1 MD0 0 0 1 0 1 1 Input # of Ports 32 16 16 Input Data Rate [MHz] 4.096 8.192 8.192 Output # of Output Data Ports Rate [MHz] 32 16 16 16*) 4.096 8.192 8.192 8.192
PCM Stand By; a logical 0 switches the PCM interface outputs to high impedance. Mode; these bits define the chip operation mode according to the following table:
Note: *) In mode 3 the PCM lines OUT(n+16) drive the inverted values of lines OUT(n) or are tristated, if the corresponding PCM line is tristated.
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Detailed Register Description 4.3 Command Register (CMDR) 01H 00H (not readable) Bit 0 FSAD2 FSAD1 FSAD0 SFE STP2 STP1 STP0
Access in demultiplexed P-interface mode: Write, address: Reset Value: Bit 7 0 FSAD2..0
Frame Synchronization signal Address 2 to 0; Address of the chosen FS signal 5 to 0 to be evaluated by the procedure started by SFE. Start Frame Evaluation; a one in this bit position starts the frame evaluation procedure. A read operation on register FER will stop an unfinished frame evaluation procedure. Start Procedure. The following procedures can be activated by these bits:
SFE
STP2..0 Table 10 STP Commands STP2 X X 0 1 X: don't care
STP1 X 0 1 1
STP0 0 1 1 1
Function No operation Start control memory reset procedure Start selftest procedure (1st part) Start selftest procedure (2nd part)
Note: Before activating one of these procedures MODR:PSB has to be set to 0. During selftest or CM reset the device will ignore the external synchronization pulse and the user has no access to the internal data memory.
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Detailed Register Description 4.4 Status Register (STAR) 01H 01H Bit 0 FSAD2 FSAD1 FSAD0 MAC PACT PSS STOK
Access in demultiplexed P-interface mode: Read, address: Reset value: Bit 7 0 FSAD2..0 MAC
Frame Synchronization signal Address: see CMDR. Memory Access Active; an indirect memory access is active, if this bit is "1", all memory access registers must not be written until MAC = "0". Procedure Active; one of the procedures started by the P (selftest, CM reset or frame evaluation) is active. PCM Synchronization Status 1: the PCM interface is synchronized 0: the PCM interface is not synchronized. (see note in chapter 4.5) Selftest O.K.; after a selftest procedure this bit is set to 1, if no faults are detected.
PACT PSS
STOK
Note: This bit is only valid, if no power failure or inappropriate clocking occurred during the test (see ISTA:IR); this bit is set to 1 by a start selftest command or by hardware reset.
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Detailed Register Description 4.5 Interrupt Status Register (ISTA) 02H 00H Bit 0 0 0 0 FEC PC IR PFI
Access in demultiplexed P-interface mode: Read, address: Reset value: Bit 7 0 FEC PC IR
Frame Evaluation Completed; the indirect register FER contains a valid offset and can be read. Procedure Completed; the procedure started from the command register (CM reset or MTSXL selftest) is finished. Initialization Request. The connection memory has to be programmed due to a loss of data (IR = 1). The IR bit is set after power failure or inappropriate clocking. It can only be retriggered again after a selftest or CM reset procedure. PCM Framing Interrupt; this bit being logical 1 indicates the loss or gain of synchronization. Synchronization is considered lost by the MTSXL if the SP signal is not repeated within the correct period. Synchronization is considered achieved, if two consecutive SP pulses with the correct period have been received.
PFI
Any interrupt will activate the INT line if it is not masked. All interrupt bits and the INT line are reset when reading ISTA.
Note 1: All interrupts and the INT line are cleared with reset. Note 2: If the SP signal is repeated within a multiple of frame length (e.g. 2 x or 4 x 125 s) but at correct phase: - the MTSXL works correctly because the internal counters run autonomously and are synchronized within correct phase. - the PFI interrupt does not occur because this situation is internally handled as "loss of synchronization" and this situation does not change. Note 3: During selftest no PFI interrupt will occur.
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Detailed Register Description 4.6 Mask Register (MASK) 02H 0FH Bit 0 0 0 0 FEC PC IR PFI
Access in demultiplexed P-interface mode: Write, address: Reset value: Bit 7 0
A logical 1 disables the corresponding interrupt as described in ISTA from activating the INT pin. A masked interrupt (bit set to "1") is stored internally and indicated, when reading ISTA. It is also reset in this case. 4.7 Memory Access Address/Code Register High (MACH) 04H 0XH Bit 0 MAC1 MAC0 0 0 MA10 MA9 MA8
Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 MAC2
A write access (rising edge of WR or CS) to this register starts an indirect access to a memory location. MAC2..0 Memory Access Code values to determine the type of access to/from control and data memory locations. See table 11 for all possible code values.
Table 11 Memory Access Codes MAC2 MAC1 MAC0 Function Max. Access Time Clock Periods - No operation Write control memory 4.5 Write & read control memory 6.5 Read control memory 4.5 Read data memory 8.5
0 0 0 0 0 1 1 0 1 0 0 1 0 0 1 All other combinations are not allowed
Note: A write & read control memory command actually writes a specific CM location and reads the same location in a second access.
MA10..8 Memory Address (most significant) bits 10 to 8; refer to register MAAL
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Detailed Register Description 4.8 Memory Access Address Register Low (MAAL) 03H XXH Bit 0 MA6 MA5 MA4 MA3 MA2 MA1 MA0
Access in a demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 MA7 MA7..0
Memory Address bits 7 to 0; the complete memory address is the concatenation of MA10..0.
If the value MA(10:0) is used as a control memory address, each address corresponds to a single output time slot (see table 12): Table 12 Output Time Slot Mapping
Mode Valid for Output (Ports) MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 Time Slot Number Port Number OUT (31:0) = Port (31:0)
0
1
MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 Time Slot Number6..1 PN3 TS0 PN2..0
OUT (7:0) = Port (7:0) OUT (23:16) = Port (15:8) OUT (7:0) = Port (7:0) = Port (15:8) OUT (23:16) = Port (15:8) = Port (31:24)
3
MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 Time Slot Number6..1 PN3 TS0 PN2..0
Note: Port(m) means, that this port drives the inverted data values of port (m-8). For the operation "Read Data Memory" MA10..0 are used as data memory addresses with the same mapping to the input time slots as listed in the above table.
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Detailed Register Description 4.9 Memory Read Data Register Low (MRDL) 05H XXH Bit 0 MRD6 MRD5 MRD4 MRD3 MRD2 MRD1 MRD0
Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 MRD7 MRD7..0 4.10
Memory Read Data values (bits 7 to 0); see MRDH;
Memory Read Data Register High (MRDH) 06H 0XH Bit 0 0 0 0 MRD11 MRD10 MRD9 MRD8
Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 0 MRD11..8
Memory Read Data values (bits 11 to 8); in a read memory access the requested values can be read in these registers after the access time (see table 11). An active access cycle, started by a write access to MACH, is indicated by register bit STAR:MAC.
4.11
Memory Write Data Register Low (MWDL) 07H XXH Bit 0
Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7
MWD7 MWD6 MWD5 MWD4 MWD3 MWD2 MWD1 MWD0 MWD7..0 Memory Write Data values (bits 7 to 0); see MWDH;
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Detailed Register Description 4.12 Memory Write Data Register High (MWDH) 08H XXH Bit 0 0 0 0 MWD11 MWD10 MWD9 MWD8
Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 0 MWD11..8
Memory Write Data values (bits 11 to 8); in a write memory access the values to transfer are written to these registers. Both registers must not be written during an active access. An active access cycle, started by a write access to MACH, is indicated by register bit STAR:MAC.
If the values MWD10..0 / MRD10..0 are used as control memory entries, each possible value corresponds to a single input time slot. MWD11 / MRD11 defines, whether the input time slot is switched actively to the PCM output or is switched to high impedance. Table 13 Input Time Slot Mapping / Programming of Output Tristate Control
Mode MRD11..0 / MWD11..0
Valid for Inputs/(Ports)
D3 D2 D1 D0 IN (31:0) = Port (31:0)
0
D11 D10 D9 TSC
D8
D7
D6
D5
D4
Time Slot Number
Port Number
1, 3
D11 D10 D9 TSC
D8
D7
D6
D5
D4
D3
D2
D1 PN2..0
D0
Time Slot Number 6..1
PN3 TS0
IN (23:16) = Port (15:8) IN (7:0) = Port (7:0)
TSC
Tristate Control Value 0: active 1: high impedance; TSC controls whether the output time slot (corresponding to the address of the control memory location) will drive the PCM values or will be tristate.
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Detailed Register Description 4.13 Input Clock Shift Register Bank ICSR (15:0) 10H...1FH 00H Bit 0 0 ICS4 ICS3 ICS2 ICS1 ICS0 RRE
Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 ADRS ADSR
Add Shift Register; a three bit shift register is inserted into the corresponding input(s), resulting in an additional offset for that/those input(s). The sampling point is shifted "backwards" by 3 clock cycles (see figure 9).
Note: ADSR has to be set to "0" in modes 1 and 3.
ICS4..0 Input Clock Shift; the value of ICS4..0 determines the number of clock cycles by which the bit sampling point is shifted forward in all input modes according to figure 9. Receive on Rising Edge; the PCM data of the corresponding input(s) is sampled with the rising edge of the clock, if this bit is set.
RRE
These 16 registers determine the individual clock shift of inputs IN0 to IN15. If more than sixteen inputs are used, two inputs are controlled by one ICSR register: ICSR0 ICSR1 ICSR2 . . ICSR7 ICSR8 ICSR9 ICSR10 . . ICSR15 " " " " " controls " " IN0, IN8 IN1, IN9 IN2, IN10 . . IN7, IN15 IN16, IN24 IN17, IN25 IN18, IN16 . . IN23, IN31
The values of ICSR (15:0) can be adjusted without producing bit errors: - clockrate = 2 x datarate possible adjustment is one half clock period forward or backward. - clockrate = 4 x datarate possible adjustment is one clock period backward or two clock periods forward.
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Detailed Register Description 4.14 Output Clock Shift Register (OSCR) 0BH 00H Bit 0 VN0 OCS4 OCS3 OCS2 OCS1 OCS0 XFE
Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 VN1 VN1..0
Version Number according to the table below: (read only) Table 14 VN 1 0 Version Number VN 0 1 Device Versions A1 (V1.2)
OCS4..0 XFE
Output Clock Shift; these values determine the offset of the output data relative to the SP frame according to figure 10. Transmit on Falling Edge 0: output data is transmitted with the rising edge of the clock. 1: output data is transmitted with the falling edge of the clock.
4.15
Test Register (TSTR) 0CH C0H Bit 0 0 0 0 0 0 DOA
Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 STOK1 STOK0 read only STOK1..0 DOA Selftest OK Data Memory; these bits are "ANDed" for STAR:STOK and can be used for analysis. Direct Output Addressing; if this bit is set to "1" the PCM outputs are not switched from the PCM inputs. Instead the 8 LSB's programmed to the connection memory are used as data bits, which are shifted out of the corresponding output time slot. The programmed tristate control value keeps its function as in normal operation mode.
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Detailed Register Description 4.16 Frame Evaluation Register Low (FERL) 0EH XXH Bit 0 FEV6 FEV5 FEV4 FEV3 FEV2 FEV1 FEV0
Access in a demultiplexed P-interface mode: Read, address: Reset value: Bit 7 FEV7 FEV7..0 4.17
Frame Evaluation Values (bits 7 to 0); refer to FERH; Frame Evaluation Register High (FERH) 0FH XXH Bit 0 0 0 0 FEV11 FEV10 FEV9 FEV8
Access in demultiplexed P-interface mode: Read, address: Reset value: Bit 7 0 FEV11..0
Frame Evaluation Values; after a frame evaluation procedure (interrupt ISTA:FEC) these two registers contain the offset between the SP frame and an evaluated FS0 ... FS5 frame. The evaluation is performed at the second following rising edge of FS after the command CMDR:SFE = 1 was programmed.
Note: The device must be synchronized to SP (STAR: PSS = 1) in order to generate a correct result in FERL / FERH.
Table 15 Frame Evaluation Register CLK / 1.024 MHz Offset Value = FEV11..1 16 FEV0 FS Rising Edge between Clock rising edge-X ns and clock falling edge-X ns Number of clock periods +1 0
Number of clock periods +1 1
Clock falling edge-X ns and clock rising edge-X ns
Note: Time constant "X" is specified to 0 ns < X < 13 ns (see figure 8)
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Electrical Characteristics 5 Electrical Characteristics
Table 16 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Supply voltage Input voltage Output voltage Symbol Limit Values 0 to 70 - 65 to 150 - 0.3 to 7.0 - 0.3 to VDD + 0.3 (max 7) - 0.3 to VDD + 0.3 (max 7) Unit C C V V V
TA Tstg VDD VI VO
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to conditions beyond those indicated in recommended operational conditions of this specification may affect device reliability.
Table 17 DC Characteristics Ambient temperature under bias range; VDD = 5 V + 5 %, VSS = 0 V Parameter L-input voltage H-input voltage L-output voltage H-output voltage H-output voltage Operational power supply current Symbol Limit Values min. max. 0.8 0.45 2.4 V V V V 100 mA - 0.4 2.0 Unit Test Condition
VIL VIH VOL VOH VOH ICC
VDD + 0.4 V IOL = 2 mA IOH = - 400 A IOH = - 100 A VDD = 5 V,
inputs at 0 V or VDD, no output loads fCLK = 16.384 MHz 0 V < VIN < VDD to 0 V 0 V < VOUT < VDD to 0 V
VDD - 0.5
Input leakage current Output leakage current
ILI ILO
1 1
A A
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Electrical Characteristics Table 18 Capacitances TA = 25 C, VDD = 5 V + 5 %, VSS = 0 V Parameter Symbol min. Input capacitance Output capacitance I/O capacitance Limit Values max. 5 10 15 pF pF pF Unit
CIN COUT CIO
AC Characteristics Ambient temperature under bias range, VDD = 5 V + 5 %. Inputs are driven at 2.4 V for a logical 1 and at 0.4 V for a logical 0. Timing measurements are made at 2.0 V for a logical 1 and at 0.8 V for a logical 0. The AC testing input/output waveforms are shown below. Timing values are guaranteed for capacitive loading of CL = 60 pF on all outputs except pins D(7:0), which are specified for CL = 100 pF.
Figure 14 I/O Waveform for AC Tests
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Electrical Characteristics Table 19 P Interface Timing Parameters Parameter Address setup time to WR, RD Address hold time from WR, RD RD pulse width Data output delay from RD x CS Data float from RD RD control interval WR pulse width Data setup time to WR x CS Data hold time from WR x CS WR control interval INT activation delay INT activation/deactivation delay from RD, WR Symbol Limit Values min. max. ns ns ns 100 25 70 60 30 10 70 100 120 ns ns ns ns ns ns ns ns ns 10 0 120 Unit
tAS tAH tRR tRD tDF tRI tWW tDW tWD tWI tID tIID
Figure 15 P Read Cycle
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Figure 16 P Write Cycle
Figure 17 Demultiplexed Address Timing
Figure 18 Interrupt Timing
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Electrical Characteristics Table 20 Parameter Clock period Clock period low Clock period high Frame setup time Frame hold time Serial data input setup time Serial data input hold time PCM serial data output delay time PCM Interface Characteristics Symbol Limit Values min. max. ns ns ns ns ns ns ns 50 ns 60 27 27 7 20 9 20 Unit Condition
tCP tCPL tCPH tFS tFH tS tH tD
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Figure 19 AC Characteristics at the PCM Interface
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Electrical Characteristics Table 21 Boundary Scan Timing Parameter Test clock period Test clock period low Test clock period high TMS setup time to TCK TMS hold time from TCK TDI setup time to TCK TDI hold time from TCK TDO delay from TCK Symbol Limit Values min. max. ns ns ns ns ns ns ns 60 ns 160 80 80 30 30 30 30 Unit Condition
tTCP tTCPL tTCPH tMSS tMSH tDIS tDIH tDOD
Figure 20 AC Characteristics at Boundary Scan Interface
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Package Outlines 6 Package Outlines P-MQFP-100-2 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 51
Dimensions in mm 03.97
GPR05365

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